1. Field of the Invention
The present invention relates to semiconductors, and in particular, to methods and structures for selectively removing stressed liners to relieve mechanical stresses.
2. Description of Related Art
It is known that mechanical stresses can modulate performance of a semiconductor device, such as, a metal-oxide-semiconductor field effect transistor (MOSFET), for enhancing the characteristics thereof. In particular, it is known that the electron mobility of an n-type MOSFET (NFET) formed on silicon with a (001) surface orientation is enhanced when tensile stress is applied in the direction of current flow (e.g. longitudinal stress) and/or in the direction perpendicular to, but in the plane of current flow (e.g. transverse stress), and/or when compressive stress is applied in the direction normal to the plane of current flow (e.g. vertical stress) in the MOSFET channel. In addition, it is known that the hole mobility of a p-type MOSFET (PFET) formed on silicon with surface oriented in the (001) crystal plane, and <110> gate orientation is enhanced when a compressive longitudinal stress is applied, and/or when tensile transverse or vertical stresses are applied in the MOSFET channel.
To selectively create tensile stress in an NFET and compressive stress in a PFET, distinctive processes and different combinations of materials are used. Again, this is because the type of stress that is beneficial for the performance of an NFET is generally disadvantageous for the performance of the PFET formed in the same substrate. For instance, when a device is in tension (in the direction of current flow in a planar device), the performance characteristics of the NFET are enhanced, while the performance characteristics of the PFET are diminished.
Previous attempts at creating mechanical stresses for enhanced device performance have required NFET and PFET devices to be individually optimized, either to enhance both NFET and PFET, or to enhance one while minimizing the degradation of the other. These prior art approaches include numerous processing steps to form trench isolation structures that include dual stress liners. These dual stress liners typically include a first stress layer in the NFET regions made from a first sequence of steps, followed by second stress layer in the PFET regions made from another sequence of steps. Other known approaches include those that add stressed layers directly on top of the MOSFET for selectively inducing the appropriate strains in the channels of the FET devices.
While these methods do provide structures that have tensile stresses being applied to the NFET device and the compressive stresses being applied along the longitudinal direction of the PFET device, they often require numerous additional processing steps, additional materials, and/or more complex processing. Overall, the disadvantages of the prior art approaches is that they are time consuming and expensive. Further, in many cost sensitive applications, it is more advantageous to enhance the NFET (PFET), while only mitigating the degradation of the PFET (NFET), if such a solution could be realized at low cost/complexity. Thus, it is desired to provide more cost-effective and simplified methods for creating large tensile and compressive stresses in the channels of NFETs and PFETs, respectively.